Design and Analysis of 128x128 arrays of SRAM cells

Memory arrays are an essential building block of all digital systems. In this project, I designed an SRAM array that contains 128 128-bit words and just layout and simulated a 128x128 array of SRAM cells, ignoring the sense-amp, and address decoders. This project has two phases.

In the first phase, 6T SRAM cell is layout and simulation results show that the cell works. The goal is to create a cell that is small and tileable (to save more area when creating an array). For laying out the cell, L-Edit is used and for simulation I used, H-Spice. Moreover, in this project, “65nm style” is used. After laying out the cell, by daring the butterfly diagram of my cell (sweep the voltages in Spice), the correct work of this cell studied. Also, two more butterfly diagrams for cases where the Vth of the hold NMOS transistors (and not the access transistors) is set to Vth*1.1 and Vth*0.9 is drawn to see what happens to the read noise margins if the Vth changes (the transistors connecting the cell to the bitlines are called access transistors, and the other two nmos transistors are called the hold transistors).


Figure. 1.   

6T SRAM Layout


Figure. 2.   

The butterfly diagram for Nmos Transistors


In the second phase, the layout of a row and a column of the array create and the worst-case delay of the word line (WL) and bitline (BL), represented. Simulation results show the delay of the memory. Furthermore, by using the Elmore delay model the delay of the word line estimated and compared with the simulation results. 

Figure. 3.    Effects of increasing of Vt on Static noise margin.


Technical Report:

S. Azizi, “Design and Analysis of 128x128 arrays of SRAM cells,” Final project of VLSI design course: Dr. K. Bazargan, Isfahan University of Technology, 2011.

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